发明名称 Stacked local interconnect structure and method of fabricating same
摘要 The present invention minimizes or eliminates the disadvantages associated with multilevel interconnect structures by providing a method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features. Significantly, in each of its embodiments, the method of the present invention does not require formation of contact plugs and, therefore, obviates the disadvantages associated with contact plug formation. Moreover, portions of the stacked local interconnect structures formed in each embodiment of the method of the present invention not only serve to electrically connect isolated device features but also serve to protect underlying, unrelated IC features from damage during subsequent etch steps. Therefore, the present invention also includes a method for protecting IC features from damage due to inadvertent etching of such features.
申请公布号 US6498088(B1) 申请公布日期 2002.12.24
申请号 US20000710399 申请日期 2000.11.09
申请人 MICRON TECHNOLOGY, INC. 发明人 TRIVEDI JIGISH D.
分类号 H01L21/768;H01L23/535;(IPC1-7):H01L21/476 主分类号 H01L21/768
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