| 摘要 |
<p>A semiconductor storage device in which refresh operation is not disturbed by late write and power consumption at the late write cycle is reduced. When an address ADD is switched, an address transition detection circuit (101) detects the address change. A state control circuit (102) receives the detection result from the address transition detection circuit (101), decides the operation to be performed according to an output enable signal/OE and a write enable signal/WE, and outputs one of a read instruction RS, a write instruction WS, and a refresh instruction FS. An input signal such as an address is fed according to the clock signal ACLK and an operation according to the instruction is performed.</p> |
