| 摘要 |
An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.
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