Dram technology compatible processor/memory chips

摘要

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.