PHASE LOCKED LOOP FOR RECOVERING A CLOCK SIGNAL FROM A DATA SIGNAL

摘要

The invention relates to a phase lock loop for recovering a clock signal (CL) from a data signal (DS), comprising a delay lock loop (DLL) with a non-linear, digital phase detector (DPD). The delay lock loop that is embedded in the phase lock loop acts as a linear phase detector. The inventive phase lock loop is economical to produce and is particularly suitable for use in data communications.