发明名称 METHOD FOR FORMING PATTERN, AND MANUFACTURING METHOD FOR DISPLAY USING THE SAME
摘要 <p>PROBLEM TO BE SOLVED: To solve the drawback that only volume expansion up to 0.1 o 2.0μm is realized at present, particularly application is difficult for forming a TFT having a source/drain electrode space of 4μm or more in a method using a resist for a PR processes at two times by the volume expansion of the resist by silylation treatment in conventional examples, although a cost-reduction effect is improved, when the PR processes at two times are reduced to one time on the manufacture of a semiconductor device. SOLUTION: When an organic solvent is made to immerse into a resist mask 7 and the resist mask 7 is melted and made to reflow after the first etching by the resist mask 7, a molten reflowing resist mask 13 is obtained. Since a method for forming a pattern is not accompanied by the volume contraction of the resist mask, heating is hardly required and the method is accompanied by large viscosity lowering, and moreover since the plane size of the resist mask is enlarged by a simple method before the second etching, and the resist mask can be formed with proper adhesion, thus easily forming a wiring 11 having a forward-tapered structure.</p>
申请公布号 JP2002334830(A) 申请公布日期 2002.11.22
申请号 JP20010176534 申请日期 2001.06.12
申请人 NEC KAGOSHIMA LTD 发明人 KIDO SHUSAKU
分类号 G02F1/1368;G03F7/40;G09F9/00;G09F9/30;H01L21/027;H01L21/302;H01L21/3065;H01L21/336;H01L29/786;(IPC1-7):H01L21/027;G02F1/136;H01L21/306 主分类号 G02F1/1368
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