| 摘要 |
PROBLEM TO BE SOLVED: To reduce a MISFET in gate length to be micronized, for improved degree of integration. SOLUTION: An opening 18 is provided to an n-type silicon layer 12a formed on a semiconductor substrate 1, dopants in the n-type silicon layer 12a are diffused into the semiconductor substrate 1 for the formation of an n<+> -type impurity region 12b, furthermore dopants are doped into the opening 18 to form an n<-> -type semiconductor region NM, a sidewall SW is formed on the sidewall of the opening 18, p-type dopants are doped into the opening 18 through the sidewall SW as a mask, and a conductive film is embedded in the opening 18 for the formation of a gate electrode 20a. As a result, a gate length L can be reduced by 2m, where (m) denotes the thickness of the sidewall SW, and a MISFET can be micronized and improved in degree of integration.
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