| 摘要 |
The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.
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