| 摘要 |
Each one of a plurality of processors has a data storage register and a unique identifier. A message passing network interconnects the registers and processors. Each processor can store data in each register, but can read data only from its own register. "Master" priority is arbitratively allocated to one of the processors by repetitively, for each processor which has not previously been dismissed as a master candidate and until all but one processor is dismissed as a master candidate: storing a dismissal value in the processor's register; selecting the next portion of the processor's identifier; if the selected portion corresponds to a non-dismissal value, storing the non-dismissal value in all of the registers; if the selected portion corresponds to the dismissal value and if the non-dismissal value is stored in the processor's register, dismissing the processor as a master candidate.
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