Hardware architecture for fast servicing of processor interrupts

摘要

An improved computer processor architecture in the form of an apparatus with a mirrored stack and method of using the same are provided that enable a processor to recover from an interrupt service routine in one or zero processor instruction cycles. The architecture also removes from software the burden of preserving and maintaining the processor registers upon an interrupt event, thereby improving coding efficiency and the utilization of processor time. The architecture makes it possible to extend faster servicing of interrupts for different levels of interrupt priorities and not just a specific interrupt path. Finally, the architecture provides a mechanism for speeding up CALL and RETURN instruction execution times. In an alternate embodiment, the mirrored stack apparatus is provided with interrupt control logic that has a port to the Program Counter control logic in order to drive directly an interrupt vector address.