发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit and a testing method thereof which allow the working load or the waiting time for inspector for the lot change and the number of cassettes to be reduced to improve the availability of a tester in the probe inspection of a wafer test process, especially, to make well adaptable to various types of products per prober unit. SOLUTION: A probe inspection system builds up a network of probers, testers, production specification management, test step control, test result management, etc., to improve the software of the prober. Lots A, B, C are set in cassettes (1), (2) one after another, and, if a lot is set in one cassette after the other cassette reaches the lot end, an operation of automatically executing the next lot process is repeated to enable the continuous working of the lot. Even during processing of the next lot, the lot change in a process-completed cassette and data input of the lot number, etc., are always allowed.
申请公布号 JP2002280425(A) 申请公布日期 2002.09.27
申请号 JP20010075671 申请日期 2001.03.16
申请人 HITACHI LTD;HITACHI HOKKAI SEMICONDUCTOR LTD 发明人 TAIRA TOMOHIRO
分类号 G01R31/26;G01R31/28;H01L21/66;(IPC1-7):H01L21/66 主分类号 G01R31/26
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