| 摘要 |
1,249,251. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORP. 7 Feb., 1969 [19 Feb., 1968], No. 6755/69. Heading H1K. Al or Al alloy interconnections 16 extending over a first insulating layer 12 on a semiconductor body 10 are covered by a second insulating layer 18 except where bonding pad windows are provided, where a first metal layer 20 of Ti, Ta or Mo or alloys thereof fills the window and covers the adjacent edge of the insulating layer 18 and a second metal layer 22 of Au or Au alloy covers the first metal layer 20. The interconnection layer 16 contacts selected regions of the body 10 through apertures in the layer 12. In the embodiment the body 10 is of Si having thereon a thermally grown oxide layer 12, and optionally a further layer of silicon nitride. The Al interconnection layer 16 is formed by a slow shuttering evaporation technique in which the initial and final portions of Al evaporated from a source are prevented by a shutter from impinging upon the body 10. The Al surface is cleaned by etching and a SiO 2 glass layer 18 is deposited by decomposition of silane. Alternatively the layer 18 may be of R.F. sputtered quartz or vapour deposited silicon oxide, quartz or "Pyrex" glass (Registered Trade Mark). The layers 20 and 22 are also evaporated on and the unrequired portions of these layers are removed by selective etching. An Au wire 24 may be compression bonded to the layer 22, or alternatively an additional thickness of plated Au and/or a dip-coated layer of Sn-Pb solder may be applied thereto to enable the arrangement to be bonded face down to a conductive track on a support. |
