发明名称 Fabrication method of semiconductor integrated circuit device and testing method
摘要 Semiconductor integrated circuit device fabricating method and testing method are provided. A probe inspection system is used wherein a network including probers, testers, manufacturing specification management, testing step control and test results management is constructed and which has a modified prober software. Lots are set successively to cassettes, and when the lot in the other cassette is set after the end of processing of the lot in one cassette, the processing of the next lot is executed automatically. A continuous lot inspection can be effected by repeating these operations. Even during processing of the next lot, it is always possible to change lot in the processing-completed cassette and input data such as lot No. In probe check in a wafer testing step it is possible to diminish the working load and wait of workers in lot change, reduce the number of cassettes and improve the working efficiency of testers. Particularly, application to a variety of items in the unit of prober can be done in a satisfactory manner.
申请公布号 US2002132381(A1) 申请公布日期 2002.09.19
申请号 US20020096801 申请日期 2002.03.14
申请人 TAIRA TOMOHIRO 发明人 TAIRA TOMOHIRO
分类号 G01R31/26;G01R31/28;H01L21/66;(IPC1-7):H01L21/66;H01L21/332 主分类号 G01R31/26
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