发明名称 |
DRAM cell configuration and fabrication method |
摘要 |
The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.
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申请公布号 |
US6448600(B1) |
申请公布日期 |
2002.09.10 |
申请号 |
US20000713484 |
申请日期 |
2000.11.15 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
SCHLOESSER TILL;HOFMANN FRANZ;WILLER JOSEF |
分类号 |
H01L27/108;H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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