| 摘要 |
A byte-switch structure for electrically erasable and programmable non-volatile memories, includes a MOS transistor having a drain electrode coupled to a respective metal control gate line, a source electrode coupled to a respective polysilicon byte control line which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line. The source and drain electrodes of the MOS transistor are respectively a first and a second doped regions of a first conductivity type formed in a semiconductor layer of a second conductivity type at opposite sides of the respective word line. The first and second doped regions are formed under the respective metal control gate line, and the polysilicon byte control gate line insulatively extends under the metal control gate line to overlap said first doped region, and contacts the first doped region through a respective contact opening in an underlying stack formed by an interpoly dielectric layer, a lower polysilicon layer and an oxide layer.
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