| 摘要 |
PROBLEM TO BE SOLVED: To eliminate signal delay difference between the respective bits which is to be caused by increase of adjacent wiring capacitance. SOLUTION: In an integrated circuit device wherein a plurality of signal lines are arranged in parallel as a bus wiring, length of signal wirings of bits at both ends of the bus wiring is made longer than that of signal wirings of the other bits, or an artificial wiring is arranged in parallel to the signal wirings of bits at both of the ends of the bus wiring, or a delay means for adjusting signal delay between the signal wirings is connected with a signal receiving side of the bus wiring, or driving ability of a driver to be connected with the signal wirings of bits at both of the ends of the bus wiring is made greater than that to be connected with signal wirings of the other bits. |
