发明名称 |
Row selection circuit for fast memory devices |
摘要 |
The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.
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申请公布号 |
US6442072(B2) |
申请公布日期 |
2002.08.27 |
申请号 |
US20000745286 |
申请日期 |
2000.12.21 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SOLIMENE RAFFAELE |
分类号 |
G11C8/08;G11C8/10;G11C16/08;G11C16/32;(IPC1-7):G11C11/34 |
主分类号 |
G11C8/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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