发明名称 Method and apparatus for layout-constrained global routing
摘要 A global router uses an algorithm for controlling routing based upon rough topologies. In one embodiment a set of regions and layers is specified over which the routing must occur. Tunnels can be defined outside of which routing cannot occur. Topologies of previous iterations are considered. Restrictions on the amount of deviation between successive iterations can be specified. As a result, successive iterations of the global router do not cause large changes in the timing delays of circuits. In addition, partial tunnels can be stretched to accommodate nearby nets. Also described are an integrated circuit that is produced using the layout-constrained global routing algorithm and a computer-readable medium storing computer-executable instructions and at least one data structure for implementing the algorithm.
申请公布号 US6442745(B1) 申请公布日期 2002.08.27
申请号 US19990474712 申请日期 1999.12.29
申请人 INTEL CORPORATION 发明人 ARUNACHALAM PRAKASH S.;CHAN HEMING
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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