Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words

摘要

A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.