CACHE SYSTEM CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To improve the performance of a microprocessor by preventing the occurrence of an unnecessary stall state as far as possible to accelerate reorder of a command. SOLUTION: This cache system control circuit is provided with a store queue 9 having plural stages, and a data cache capable of reordering a command. The cache system control circuit processes a command accompanied with tag detection even when a store command exists in the store queue 9 and an index of the commend accompanied with the following tag detection coincides with an index of the store command in the store queue 9. Only when the command accompanied with the tag detection causes a cache miss and at least one combination of indexes and ways to be replaced and one combination of indexes and ways of the store command in the store queue 9 is coincided with each other, replacing for canceling the cache miss is carried out after conducting writing by the store command in the store queue 9.