| 摘要 |
PROBLEM TO BE SOLVED: To provide a reliable SRAM device. SOLUTION: Two pairs of bit lines (BLa and BLa) and (BLb and BLb) for an A port and a B port are disposed on P wells 2a and 2b respectively with an N well 1 interposed between the P wells 2a and 2b, with the bit lines in each pair separated from each other. Due to this structure, even if the A port and the B port are operated completely asynchronously with each other, the influence by interconnection coupling between the pairs of bit lines can be suppressed or prevented. |
