Computationally efficient modular multiplication method and apparatus

摘要

A computationally efficient multiplication method and apparatus for modular exponentiation. The apparatus uses a preload register, coupled to a multiplier at a second input port via a KN bit bus to load the value of the "a" multiplicand in the multiplier in a single clock pulse. The "b" multiplicand (which is also KN bits long) is supplied to the multiplier N bits at a time from a memory output port via an N bit bus coupled to a multiplier first input port. The multiplier multiplies the N bits of the "b" multiplicand by the KN bits of the "a" multiplicand and provides that product at a multiplier output N bits at a time, where it can be supplied to the memory via a memory input port.