发明名称 Method of manufacturing ferroelectric memory device
摘要 A method of manufacturing a ferroelectric memory device which has a gate structure constituted by a ferroelectric layer and a conductor layer stacked on a semiconductor substrate. The method includes steps of forming the gate structure section by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities thereby to form a pair of impurity diffused layers.
申请公布号 US2002098599(A1) 申请公布日期 2002.07.25
申请号 US20020108381 申请日期 2002.03.29
申请人 TAKASU HIDEMI;NAKAMURA TAKASHI 发明人 TAKASU HIDEMI;NAKAMURA TAKASHI
分类号 H01L21/8247;H01L21/28;H01L21/336;H01L21/8246;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/00 主分类号 H01L21/8247
代理机构 代理人
主权项
地址
您可能感兴趣的专利