发明名称 |
Mask revision ID code circuit |
摘要 |
A mask identification (ID) bit circuit (100) is disclosed that provides one of two potentials (VGND or VPWR) to a sense node (108). A mask ID bit circuit (100) may include a number of links (102-0 to 102-4) arranged in series. A link (102-0 to 102-4) may include inputs (104-0 and 104-1) and outputs (106-0 and 106-1). In one configuration, inputs (104-0 and 104-1) may be directly coupled to outputs (106-0 and 106-1). In another configuration, inputs (104-0 and 104-1) may be cross coupled to outputs (106-0 and 106-1). Cross coupling inputs (104-0 and 104-1) and outputs (106-0 and 106-1) of a link (102-0 to 102-4) can switch a potential (VGND or VPWR) supplied to a sense node (108). The configuration of more than one link (102-0 to 102-4) of a mask ID bit circuit (100) can be changed, allowing a sense node to be switched between two potential (VGND and VPWR) multiple times. According to an embodiment, n mask ID bit circuits (100) may provide as many as 2n different mask ID codes.
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申请公布号 |
US2002084331(A1) |
申请公布日期 |
2002.07.04 |
申请号 |
US20000751429 |
申请日期 |
2000.12.29 |
申请人 |
REINSCHMIDT ROBERT M.;CHOI RONALD W. |
发明人 |
REINSCHMIDT ROBERT M.;CHOI RONALD W. |
分类号 |
G03F1/14;G06K19/067;H01L23/544;(IPC1-7):G06K19/00 |
主分类号 |
G03F1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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