发明名称 |
Method and apparatus for transistor optimization, method and apparatus for layout design of integrated circuit, and integrated circuit |
摘要 |
In designing an integrated circuit, the size of a transistor is optimized together with the folding number thereof. The optimization of the size and folding number of the transistor is accomplished by using a folding model in which a plurality of folding numbers are assumed for one transistor size. In the folding model, if the lower limit value of the transistor size W is W0 and the height of a placement region for the transistor is H0, the folding number N can be determined arbitrarily so long as W/H0<=N<=W/W0 is satisfied. If the size of the transistor is optimized together with the folding number thereof by using the folding model so long as a given design constraint is satisfied, there can be designed an integrated circuit which has been improved in terms of area and performance.
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申请公布号 |
US6415417(B1) |
申请公布日期 |
2002.07.02 |
申请号 |
US20000516779 |
申请日期 |
2000.03.01 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TANAKA MASAKAZU;FUKUI MASAHIRO |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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