| 发明名称 |
Damascene cap layer process for integrated circuit interconnects |
| 摘要 |
The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).
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| 申请公布号 |
US6410426(B1) |
申请公布日期 |
2002.06.25 |
| 申请号 |
US20010901392 |
申请日期 |
2001.07.09 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
XING GUOQIANG;JIANG PING |
| 分类号 |
H01L21/3065;H01L21/4763;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/3065 |
| 代理机构 |
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