| 摘要 |
Specific sequence circuit element detector 4 detects each sequential circuit element having a clock control terminal connected to an output node of a clock tree synthesis and an output terminal connected, directly or via a combinational circuit element, to one of output terminals designated by output terminal list 3 from logical connection information 1 and logical element library 2. Clock signal replacer 5 replaces the output node of the clock tree synthesis connected to the clock control terminal by an input node of the clock tree synthesis and generates logical connection information 6 logically equivalent to logical connection information 1.
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