| 摘要 |
<p>The frequency synthesizer comprises a double-module frequency divider (102) with one input for a signal of frequency (fvco) for division from a voltage-controlled oscillator and the other input for a fractional-division control signal from a control module (108), a phase/frequency detector/comparator (12) which compares the phase of signal from the frequency divider received by the intermediary of the main-part computing unit (106) to the phase of a reference-frequency (fref) signal received by the intermediary of a reference divider (110), and a digital sigma-delta modulator (118) whose single-bit output is connected jointly to the computing units (104,106) by the intermediary of a bits converter (116) for the fractional-division control of the double-module frequency divider. An output of the phase comparator is connected to the control input of the voltage-controlled oscillator to form a phase-locked loop. The main-part (B) computing unit (106) and the residual-part (A) computing unit (104) have the inputs connected to the output of the double-module frequency divider (102), and the outputs connected to the control module (108). The sigma-delta modulator (118) contains n-stage accumulator circuit cascade, where each stage comprises a coefficient generator, an adder and an accumulataor, also weighting coefficient generators between stages, and a quantifier circuit providing the single-bit output. The noise-transfer function (NTF) of the sigma-delta modulator is H(z) = (1-z->1>)n/D(z), where D(z) is a polynomial of degree n with real coefficients, where n is at least equal to 2, e.g. n = 4.</p> |
