| 摘要 |
PURPOSE: A sensing control circuit and a layout of a semiconductor memory device are provided, which improves a sensing speed and reduces a layout area by realizing a power transistor of sufficient size by arranging the power transistor of a sense amplifier in the sense amplifier. CONSTITUTION: Between a pair of cell arrays(100,124), the first equalizer circuit(102), the first isolation circuit(104), the first PMOS sense transistor(106), the first power transistor(108), the second PMOS sense transistor(110), a CSL circuit(112), the first NMOS sense transistor(114), the second power transistor(116), the second NMOS sense transistor(118), the second isolation circuit(120) and the second equalizer circuit(124) are arranged in sequence along a pair of horizontal bit lines(BL,BLB). That is, the power transistors are arranged between sense transistors. According to the layout, a power contact is arranged between the two bit lines, and a power gate is arranged around the power contact. And a number of sense transistor gates are arranged around the power gate. A pair of control line contacts are arranged in the outside of the bit lines, and a control line is connected to the power gate through the control line contact. And a power line is connected to an active region surrounded by the power gate through the power contact.
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