| 摘要 |
In a flat bed type scanner, while a control unit (24) for generating a secondary control signal and for controlling a CCD (22) is separated from an image processing ASIC (46) for generating a primary clock signal as a base signal of the secondary control signal, this scanner is arranged so as to generate the secondary control signal having the short pulse width from the primary clock signal having the long pulse width. This scanner employs such an arrangement that the primary clock signal having the long pulse width is transmitted via an FFC (40) which electrically connects the image processing ASIC (46) with the control unit (24).
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