发明名称 MEMORY CONTROL DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a memory control device which is improved in a processing speed by giving a temporal limitation to the switching operation of a bank in a buffer when writing the data given from a CPU in a memory. SOLUTION: When the bank with data written thereon comes into a memory full state in the buffer 2 or there is no data input till a predetermined time passes after the data is written in this bank, a buffer control part 3 makes readable a writing bank and also makes a next bank for use in writing. When all the data stored in the reading bank is read out in the buffer 2, the buffer control part 3 makes writable the reading bank and also makes a next bank for use in reading.
申请公布号 JP2002132572(A) 申请公布日期 2002.05.10
申请号 JP20000319213 申请日期 2000.10.19
申请人 SANYO ELECTRIC CO LTD 发明人 HIRAMATSU TATSUO;SAITO SATORU
分类号 G06F12/00;(IPC1-7):G06F12/00 主分类号 G06F12/00
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