| 摘要 |
An architecture for video decompressor to efficiently access a synchronously memory includes a synchronous memory device (11) having an A-bank and B-bank for being stored with image data, and a memory controller (12) for controlling data access to the synchronous memory to peform motion compensation and display. The image data has a plurality of scan lines (L0, L1, L2..) and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N + 0)-th and (4N + 1)-th scan lines, and the B-bank is sequentially stored with the (4N + 2)-th and (4N + 3)-th scan lines, where N is a non-negative integer, so as to always perform memory operations by alternatively accessing the A-bank and B-bank. The scan lines may be grouped every eight scan lines. |
