| 摘要 |
A method is disclosed including generating a digital control signal having a duty cycle which varies randomly or pseudo-randomly between a number of cycles, and is substantially fixed when averaged over the cycles. A target signal such as a digital clock signal may be passed selectively, in accordance with the control signal. A particular application of the method is power management in computers and other electronic systems that feature high performance processor and memory configurations that involve synchronous accesses of the memory by the processor.
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