发明名称 |
Method of locally forming metal silicide layers |
摘要 |
The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line.The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.
|
申请公布号 |
US6372640(B1) |
申请公布日期 |
2002.04.16 |
申请号 |
US20010917645 |
申请日期 |
2001.07.31 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
CHEN YING-TSO;LAI ERH-KUN;CHEN HSIN-HUEI;HWANG SHOU-WEI;HUANG YU-PING |
分类号 |
H01L21/285;H01L21/336;H01L21/8242;(IPC1-7):H01L21/44 |
主分类号 |
H01L21/285 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|