发明名称 SELF-ORTHOGONAL CODING/DECODING CIRCUIT AND SELF- ORTHOGONAL CODING/DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a self orthogonal coding/decoding circuit which can greatly improve error correction capability, using a simplified circuit configuration. SOLUTION: A code synchronous and serial/parallel conversion circuit 1 synchronizes codes and converts a receiving system Y into information systems I1 to IK and a testing system P in serial and parallel, and outputs them to a first stage decoding circuit 2. The circuit 2 inputs the information systems I1 to IK and the testing system P and corrects errors on the basis of them, and then it outputs first stage first to K-th information systems I1-C1 to 1K-C1 and a delay-testing system PD to a second stage decoding circuit 3. The second stage decoding circuit 3 corrects an error in the first stage first to K-th information systems I1-C1 to IK-C1, in which errors are decreased by the first stage decoding circuit 2, so as to further cause the number of errors to be reduced.
申请公布号 JP2002111516(A) 申请公布日期 2002.04.12
申请号 JP20000293231 申请日期 2000.09.27
申请人 NEC CORP 发明人 SEKI KATSUTOSHI
分类号 G06F11/10;H03M13/23;H03M13/33;H03M13/39;(IPC1-7):H03M13/39 主分类号 G06F11/10
代理机构 代理人
主权项
地址