发明名称 DIGITAL PHASE SHIFTER
摘要 <p>After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.</p>
申请公布号 WO2002029975(A2) 申请公布日期 2002.04.11
申请号 US2001031450 申请日期 2001.10.05
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址