| 摘要 |
A sense amplifier output control circuit capable of outputting data from the sense amplifier without delaying. The sense amplifier output control circuit includes a first logical operating element receiving an inverted output of the sense amplifier and a first controlling signal; a flip-flop circuit including a second logical operating element and a third logical operating element, the second logical operating element receiving signals from the first logical operating element and the third logical operating element, and the third logical operating element receives a signal from the second logical operating element and the first controlling signal; a fourth logical operating element receiving a signal from the flip-flop circuit and a second control signal; and a fifth logical operating element for inverting a signal from the fourth logical operating element. An output terminal of the fifth logical operating element is connected to an input terminal of the sense amplifier.
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