COMPARATOR AND CACHE MEMORY

摘要

PROBLEM TO BE SOLVED: To realize a cache memory for generating a hit signal in a short time by performing comparison of all the bits of an inputted address at a high speed. SOLUTION: A tag memory is provided, for each bit, with a selector 13 for selecting and outputting either of the outputs SO, /SO of a sense amplifier 9 by each bit data (TAGADD) of an address, and an N-channel transistor 15 for gate-inputting the output of the selector 13, and is further provided with a hit signal generation part 21 having a P-channel transistor 19 whose drain is connected with the drains of all the N-channel transistors 15 and whose gate receives a pulse signal. When the output SO of the sense amplifier 9 in each selector 13 coincides with the data (TAGADD) of the address, the N- channel transistors 15 are turned off, and when they do not coincide with each other, the N-channel transistors 15 are turned on.