| 摘要 |
<p>In digital servo in which an output equation yd[k]=C x[k]+D ud[k], and a state equation x[k+1]=A x[k]+B ud[k] are executed, in order to reduce the average time lag that a control signal has, the second term D ud[k] (hereinafter referred to as a direct transfer term) of the output equation is outputted from an analog circuit and the first term C x[k] is outputted Ts/2 (where Ts is the basic operation cycle) early; or the direct transfer term of the output equation is executed at Ts/N (where N is a natural number of two or more) cycle and the first term is updated with the same time lag as the average time lag Ts/(2N) that the direct transfer term has; or the a0 term of a transfer equation is outputted from an analog circuit and the other terms are outputted Ts/2 early; or the a0 term of the transfer equation is executed at Ts/N cycle and the other terms are updated with the same time lag as the average time lag Ts/(2N) that the direct transfer term.</p> |
