| 摘要 |
<p>The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes and input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-shew to the data buffers and/or the memory devices.</p> |
