发明名称 |
Circuit and method for fast modular multiplication |
摘要 |
A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in an adder (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of mu as is required in the Montgomery Reduction Algorithm.
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申请公布号 |
US6356636(B1) |
申请公布日期 |
2002.03.12 |
申请号 |
US19980120580 |
申请日期 |
1998.07.22 |
申请人 |
MOTOROLA, INC. |
发明人 |
FOSTER ROBERT I.;BUSS JOHN MICHAEL;TESCH RODNEY C.;DWORKIN JAMES DOUGLAS;TORLA MICHAEL J. |
分类号 |
G06F7/72;(IPC1-7):H04L9/30 |
主分类号 |
G06F7/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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