When a processor (10) makes a request for an access to a memory (17), the request is checked if it is a write or read request. If the request is a request for a read access to the memory (17), the operating clock of the processor (10) is stopped for a predetermined number of clock cycles; in contrast, if a clock control request signal is for a write request of the processor (10) to the memory (17), the operating clock of the processor (10) is not stopped.
申请公布号
WO0219113(A1)
申请公布日期
2002.03.07
申请号
WO2001JP06720
申请日期
2001.08.06
申请人
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;IKEDA, TETSUYA;SAWAI, TOSHITSUGU;OKAMOTO, MINORU