发明名称 |
Cache system with limited number of tag memory accesses |
摘要 |
The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
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申请公布号 |
US2002029321(A1) |
申请公布日期 |
2002.03.07 |
申请号 |
US20010768348 |
申请日期 |
2001.01.25 |
申请人 |
EBESHU HIDETAKA;TOMATSURI HIDEAKI |
发明人 |
EBESHU HIDETAKA;TOMATSURI HIDEAKI |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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