| 摘要 |
A mask ROM device, which is synchronously operable with an external clock signal, has a single word mode or a double word mode. A word decoder and a selection circuit are provided to the mask ROM device, wherein, during a read operation of the single word mode, the word decoder holds a word signal at a disable interval of an internal clock signal earlier by 2 clock cycles than a clock cycle corresponding to a predetermined CAS latency after an occurrence of a read command, and the selection circuit transfers one of higher and lower data corresponding to columns selected by a column selection circuit to an output buffer circuit in response to selection signals generated by the word decoder, and then consecutively transfers the remaining one of the data thereto. According to such a control manner, word data can be accessed without a collision with previously outputted data, or pausing after it.
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