| 摘要 |
A method and apparatus for calibrating a pipeline stage in a multi-bit/stage pipeline A/D converter involves switching (S3, S4) a set of D/A converter unit-segments in the stage to predetermined states (+/-) for producing (S5) a first digital signal (d+), and switching (S6) a predetermined unit-segment in the set to its complementary state, keeping the states of the other unit-segments in said set unchanged, for producing (S7) a second digital signal (d-). The unit-segment is then associated (S8) with a calibration coefficient representing the deviation of the difference between the first and second digital signals from an expected difference between the first and second digital signals. This process is repeated for each unit-segment that is to be calibrated.
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