| 摘要 |
An integrated circuit device sending trace data generated by a central processing unit (CPU) to a debug device without loss and a method of controlling the operation of the integrated circuit device. The integrated circuit device has the CPU executing various types of data processing. A trace buffer is connected via a parallel bus to a predetermined output terminal of the CPU. A buffer monitoring circuit is connected to an input terminal of the trace buffer and to a predetermined control terminal of the CPU. The CPU executes various types of data processing requested by a program and outputs trace data indicating an execution history. The trace buffer temporarily stores the trace data that is output in parallel by the CPU. When a usage amount of the trace buffer exceeds a preset threshold, the buffer monitoring circuit sends an interrupt signal BRKINT to the CPU to suspend the data processing of the CPU and, when a preset period of time elapses, releases the suspension of data processing of the CPU.
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