发明名称 METHOD FABRICATING CHIP SCALE PACKAGE USING LEAD
摘要 PURPOSE: A method for fabricating a chip scale package using a lead is provided to fabricate easily a chip scale package by simplifying an existing fabrication process. CONSTITUTION: A patterned inner lead(15) is adhered on an active portion(12a) of a semiconductor chip(12) by using an adhesive tape(14). An outer lead(16) is adhered on the inner lead(15). The inner lead(15) is connected electrically with the semiconductor chip(12) by a bonding wire(17). A resin sealing portion(18) is formed by applying a resin on the whole surface of the active portion(12a) except for a back surface(12b) in order to protect the active portion(12a) of the semiconductor chip(12), the inner lead(15) formed on the active portion(12a), the outer lead(16) formed on the inner lead(15), and the bonding wire(17) from external environment. The semiconductor chip(12) is an edge pad type semiconductor chip with an electrode pad(13) formed around an edge the active portion(12a).
申请公布号 KR20020001151(A) 申请公布日期 2002.01.09
申请号 KR20000035376 申请日期 2000.06.26
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE, CHAN SEOK
分类号 H01L23/28;(IPC1-7):H01L23/28 主分类号 H01L23/28
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