发明名称 DECODER AND DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce the scale of circuit without having any effect on the results of decoding. SOLUTION: The decoder comprises an addition/comparison/selection circuit 60 for determining a correction term being added to provide a logarithmic likelihood and represented by one-dimensional function of variables and calculating a logarithmic likelihood by adding a predetermined value to the correction term such that the positive and negative identification codes of logarithmic likelihood is unified. The addition/comparison/selection circuit 60 stores the relation between absolute value data|P-Q|, i.e., the variables of the function, and the sum of the correction term and the predetermined value in an ROM 66 in the form of a table. The absolute value data|P-Q|fed from an absolute value calculating circuit 65 is read out as an address signal and a value for the absolute value data|P-Q|is read out by a difference unit 67 as data Z.
申请公布号 JP2001352256(A) 申请公布日期 2001.12.21
申请号 JP20000172677 申请日期 2000.06.08
申请人 SONY CORP 发明人 YAMAMOTO KOHEI;MIYAUCHI TOSHIYUKI
分类号 G06F11/10;H03M13/45;(IPC1-7):H03M13/45 主分类号 G06F11/10
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