| 摘要 |
The device comprises a module for the input pulse filtering formed by a generator module (1) of an analogue control signal delivering a first voltage transition on the rising analogue signal crossing a threshold value of an inverter module (2), and a calibration module in amplitude and length formed by a delay module (3) controlling the generator module (1) in switching and a second transition generator formed by the inverter module (2) on crossing the threshold value by falling analogue signal. The length of filtered and calibrated pulse is given by the time interval separating the two transitions. The device for implementation in CMOS (Complementary Metal-Oxide-Semiconductor) technology comprises an inverter branch (10) with p-MOS transistor (TP3) connected in series drain-source to n-MOS transistor (TN0), where the gates of both transistors receive the input pulse (INTRIG), a pair of n-MOS transistor (TN1) and p-MOS transistor (TP2) connected in series with the transistor (TN0) of the inverter branch, where the gates of transistors in pair receive the delayed pulse (DINTRIG). The inverter module (2) with a trigger-off threshold comprises p-MOS transistor (TP4) and n-MOS transistor (TN2) connected in series drain-source between the supply voltage (Vcc) and the reference voltage (Vref), where the gates of both transistors receive the analogue control signal from the node N1. |
