| 摘要 |
PROBLEM TO BE SOLVED: To provide a DLL circuit which can stably match a delay clock CLKD with a reference clock CLK in phase. SOLUTION: The DLL circuits has a counter control circuit 40, which is equipped with inverters 401, 403, 409, and 414, NANDs 402, 404, 405, and 408, shift registers 406, 407, 416, and 417, clocked inverters 410 to 413, and a NOR gate 415. The counter control circuit 40 when inputting an H-level reset signal RST or an address minimum signal CMIN indicating the minimum value of an address forcibly switches a signal REV to an H level to generate an H-level counter control signal and a signal EN, thereby placing a counter in forcible up mode. |
